#ifndef CYGONCE_PKGCONF_SYSTEM_H
#define CYGONCE_PKGCONF_SYSTEM_H
/*
 * File <pkgconf/system.h>
 *
 * This file is generated automatically by the configuration
 * system. It should not be edited. Any changes to this file
 * may be overwritten.
 */

#define CYGNUM_VERSION_CURRENT 0x7fffff00
#define CYGPKG_HAL_CORTEXM v3_0
#define CYGPKG_HAL_CORTEXM_v3_0
#define CYGNUM_HAL_CORTEXM_VERSION_MAJOR 3
#define CYGNUM_HAL_CORTEXM_VERSION_MINOR 0
#define CYGNUM_HAL_CORTEXM_VERSION_RELEASE -1
#define CYGPKG_HAL_CORTEXM_STM32 v3_0
#define CYGPKG_HAL_CORTEXM_STM32_v3_0
#define CYGNUM_HAL_CORTEXM_STM32_VERSION_MAJOR 3
#define CYGNUM_HAL_CORTEXM_STM32_VERSION_MINOR 0
#define CYGNUM_HAL_CORTEXM_STM32_VERSION_RELEASE -1
#define CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL v3_0
#define CYGPKG_HAL_CORTEXM_STM32_STM3210E_EVAL_v3_0
#define CYGNUM_HAL_CORTEXM_STM32_STM3210E_EVAL_VERSION_MAJOR 3
#define CYGNUM_HAL_CORTEXM_STM32_STM3210E_EVAL_VERSION_MINOR 0
#define CYGNUM_HAL_CORTEXM_STM32_STM3210E_EVAL_VERSION_RELEASE -1
#define CYGBLD_HAL_TARGET_H   <pkgconf/hal_cortexm.h>
#define CYGBLD_HAL_VARIANT_H  <pkgconf/hal_cortexm_stm32.h>
#define CYGBLD_HAL_PLATFORM_H <pkgconf/hal_cortexm_stm32_stm3210e_eval.h>
#define CYG_HAL_STARTUP ROM
#define CYG_HAL_STARTUP_ROM
#define CYGHWR_MEMORY_LAYOUT_LDI <pkgconf/mlt_cortexm_stm3210e_eval_rom.ldi>
#define CYGHWR_MEMORY_LAYOUT_H <pkgconf/mlt_cortexm_stm3210e_eval_rom.h>
#define CYGPKG_IO_SERIAL_CORTEXM_STM32 v3_0
#define CYGPKG_IO_SERIAL_CORTEXM_STM32_v3_0
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_VERSION_MAJOR 3
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_VERSION_MINOR 0
#define CYGNUM_IO_SERIAL_CORTEXM_STM32_VERSION_RELEASE -1
/***** serial driver proc output start *****/
#define CYGDAT_IO_SERIAL_DEVICE_HEADER <pkgconf/io_serial_cortexm_stm32.h>
/*****  serial driver proc output end  *****/
#define CYGPKG_IO_SPI v3_0
#define CYGPKG_IO_SPI_v3_0
#define CYGNUM_IO_SPI_VERSION_MAJOR 3
#define CYGNUM_IO_SPI_VERSION_MINOR 0
#define CYGNUM_IO_SPI_VERSION_RELEASE -1
#define CYGPKG_DEVS_SPI_CORTEXM_STM32 v3_0
#define CYGPKG_DEVS_SPI_CORTEXM_STM32_v3_0
#define CYGNUM_DEVS_SPI_CORTEXM_STM32_VERSION_MAJOR 3
#define CYGNUM_DEVS_SPI_CORTEXM_STM32_VERSION_MINOR 0
#define CYGNUM_DEVS_SPI_CORTEXM_STM32_VERSION_RELEASE -1
#define CYGPKG_IO_FLASH v3_0
#define CYGPKG_IO_FLASH_v3_0
#define CYGNUM_IO_FLASH_VERSION_MAJOR 3
#define CYGNUM_IO_FLASH_VERSION_MINOR 0
#define CYGNUM_IO_FLASH_VERSION_RELEASE -1
#define CYGPKG_DEVS_FLASH_SPI_AT25DFXXX current
#define CYGPKG_DEVS_FLASH_SPI_AT25DFXXX_current
#define CYGNUM_DEVS_FLASH_SPI_AT25DFXXX_VERSION_MAJOR CYGNUM_VERSION_CURRENT
#define CYGNUM_DEVS_FLASH_SPI_AT25DFXXX_VERSION_MINOR -1
#define CYGNUM_DEVS_FLASH_SPI_AT25DFXXX_VERSION_RELEASE -1
#define CYGPKG_IO_I2C v3_0
#define CYGPKG_IO_I2C_v3_0
#define CYGNUM_IO_I2C_VERSION_MAJOR 3
#define CYGNUM_IO_I2C_VERSION_MINOR 0
#define CYGNUM_IO_I2C_VERSION_RELEASE -1
#define CYGPKG_DEVS_I2C_CORTEXM_STM32 v3_0
#define CYGPKG_DEVS_I2C_CORTEXM_STM32_v3_0
#define CYGNUM_DEVS_I2C_CORTEXM_STM32_VERSION_MAJOR 3
#define CYGNUM_DEVS_I2C_CORTEXM_STM32_VERSION_MINOR 0
#define CYGNUM_DEVS_I2C_CORTEXM_STM32_VERSION_RELEASE -1
#define CYGPKG_HAL v3_0
#define CYGPKG_HAL_v3_0
#define CYGNUM_HAL_VERSION_MAJOR 3
#define CYGNUM_HAL_VERSION_MINOR 0
#define CYGNUM_HAL_VERSION_RELEASE -1
#define CYGPKG_IO v3_0
#define CYGPKG_IO_v3_0
#define CYGNUM_IO_VERSION_MAJOR 3
#define CYGNUM_IO_VERSION_MINOR 0
#define CYGNUM_IO_VERSION_RELEASE -1
#define CYGPKG_IO_SERIAL v3_0
#define CYGPKG_IO_SERIAL_v3_0
#define CYGNUM_IO_SERIAL_VERSION_MAJOR 3
#define CYGNUM_IO_SERIAL_VERSION_MINOR 0
#define CYGNUM_IO_SERIAL_VERSION_RELEASE -1
#define CYGPKG_INFRA v3_0
#define CYGPKG_INFRA_v3_0
#define CYGNUM_INFRA_VERSION_MAJOR 3
#define CYGNUM_INFRA_VERSION_MINOR 0
#define CYGNUM_INFRA_VERSION_RELEASE -1
#define CYGPKG_KERNEL v3_0
#define CYGPKG_KERNEL_v3_0
#define CYGNUM_KERNEL_VERSION_MAJOR 3
#define CYGNUM_KERNEL_VERSION_MINOR 0
#define CYGNUM_KERNEL_VERSION_RELEASE -1
#define CYGPKG_MEMALLOC v3_0
#define CYGPKG_MEMALLOC_v3_0
#define CYGNUM_MEMALLOC_VERSION_MAJOR 3
#define CYGNUM_MEMALLOC_VERSION_MINOR 0
#define CYGNUM_MEMALLOC_VERSION_RELEASE -1
#define CYGPKG_ISOINFRA v3_0
#define CYGPKG_ISOINFRA_v3_0
#define CYGNUM_ISOINFRA_VERSION_MAJOR 3
#define CYGNUM_ISOINFRA_VERSION_MINOR 0
#define CYGNUM_ISOINFRA_VERSION_RELEASE -1
#define CYGPKG_LIBC v3_0
#define CYGPKG_LIBC_v3_0
#define CYGNUM_LIBC_VERSION_MAJOR 3
#define CYGNUM_LIBC_VERSION_MINOR 0
#define CYGNUM_LIBC_VERSION_RELEASE -1
#define CYGPKG_LIBC_I18N v3_0
#define CYGPKG_LIBC_I18N_v3_0
#define CYGNUM_LIBC_I18N_VERSION_MAJOR 3
#define CYGNUM_LIBC_I18N_VERSION_MINOR 0
#define CYGNUM_LIBC_I18N_VERSION_RELEASE -1
#define CYGPKG_LIBC_SETJMP v3_0
#define CYGPKG_LIBC_SETJMP_v3_0
#define CYGNUM_LIBC_SETJMP_VERSION_MAJOR 3
#define CYGNUM_LIBC_SETJMP_VERSION_MINOR 0
#define CYGNUM_LIBC_SETJMP_VERSION_RELEASE -1
#define CYGPKG_LIBC_SIGNALS v3_0
#define CYGPKG_LIBC_SIGNALS_v3_0
#define CYGNUM_LIBC_SIGNALS_VERSION_MAJOR 3
#define CYGNUM_LIBC_SIGNALS_VERSION_MINOR 0
#define CYGNUM_LIBC_SIGNALS_VERSION_RELEASE -1
#define CYGPKG_LIBC_STARTUP v3_0
#define CYGPKG_LIBC_STARTUP_v3_0
#define CYGNUM_LIBC_STARTUP_VERSION_MAJOR 3
#define CYGNUM_LIBC_STARTUP_VERSION_MINOR 0
#define CYGNUM_LIBC_STARTUP_VERSION_RELEASE -1
#define CYGPKG_LIBC_STDIO v3_0
#define CYGPKG_LIBC_STDIO_v3_0
#define CYGNUM_LIBC_STDIO_VERSION_MAJOR 3
#define CYGNUM_LIBC_STDIO_VERSION_MINOR 0
#define CYGNUM_LIBC_STDIO_VERSION_RELEASE -1
#define CYGPKG_LIBC_STDLIB v3_0
#define CYGPKG_LIBC_STDLIB_v3_0
#define CYGNUM_LIBC_STDLIB_VERSION_MAJOR 3
#define CYGNUM_LIBC_STDLIB_VERSION_MINOR 0
#define CYGNUM_LIBC_STDLIB_VERSION_RELEASE -1
#define CYGPKG_LIBC_STRING v3_0
#define CYGPKG_LIBC_STRING_v3_0
#define CYGNUM_LIBC_STRING_VERSION_MAJOR 3
#define CYGNUM_LIBC_STRING_VERSION_MINOR 0
#define CYGNUM_LIBC_STRING_VERSION_RELEASE -1
#define CYGPKG_LIBC_TIME v3_0
#define CYGPKG_LIBC_TIME_v3_0
#define CYGNUM_LIBC_TIME_VERSION_MAJOR 3
#define CYGNUM_LIBC_TIME_VERSION_MINOR 0
#define CYGNUM_LIBC_TIME_VERSION_RELEASE -1
#define CYGPKG_LIBM v3_0
#define CYGPKG_LIBM_v3_0
#define CYGNUM_LIBM_VERSION_MAJOR 3
#define CYGNUM_LIBM_VERSION_MINOR 0
#define CYGNUM_LIBM_VERSION_RELEASE -1
#define CYGPKG_IO_WALLCLOCK v3_0
#define CYGPKG_IO_WALLCLOCK_v3_0
#define CYGNUM_IO_WALLCLOCK_VERSION_MAJOR 3
#define CYGNUM_IO_WALLCLOCK_VERSION_MINOR 0
#define CYGNUM_IO_WALLCLOCK_VERSION_RELEASE -1
#define CYGPKG_ERROR v3_0
#define CYGPKG_ERROR_v3_0
#define CYGNUM_ERROR_VERSION_MAJOR 3
#define CYGNUM_ERROR_VERSION_MINOR 0
#define CYGNUM_ERROR_VERSION_RELEASE -1
#define CYGPKG_POSIX v3_0
#define CYGPKG_POSIX_v3_0
#define CYGNUM_POSIX_VERSION_MAJOR 3
#define CYGNUM_POSIX_VERSION_MINOR 0
#define CYGNUM_POSIX_VERSION_RELEASE -1

#endif
